One time programming by means of electrical fuses are used on Integrated Circuits (ICs) for a variety of application including, implementation of redundant rows and columns for memory products, programming of various options or operating modes of an IC, and component value fine tuning, such as for resistors or capacitors. Other typical uses of one time programming of data are found in numerous memory storage applications including, programmable array logic (PALs), programmable logic devices, and Programmable Read Only Memories (PROMs).
Fabrication and programming of fuses on ICs has conventionally been done by constructing metal fuses that are then blown open by applying high current through the fuse. Another method is by constructing either metal or polysilicon (or poly) fuses which are blown open with a laser. Other techniques make use of floating gate technology where charge is stored on a floating gate by tunnelling electrons through an insulator.
Some big drawbacks to these conventional approaches include the following. When programming with metal fuses high current drivers or fuse blowing pads must be fabricated into the IC in order to provide or handle the high current required to blow the desired fuse. These added drivers and pads, unfortunately, take up considerable real estate on the IC die, which on memory intensive devices is very undesirable. Some disadvantages of blowing a metal or poly fuse by a laser include, very tight alignment tolerances between the laser beam and fuse, not to mention the expense of the laser itself. Both methods can leave residual splatter that may later allow the fuse to heal itself and become a resistive short thereby destroying previous programming and lowering the ICs reliability. If floating gate technology is used, a high supply voltage (typically between 10-30 V) is required to program the storage element. This means an external supply will be required for programming.
U.S. Pat. No. 4,543,594 suggests using a planar capacitor, reproduced in FIG. 1, as a fusible link. As FIG. 1 shows the planar capacitor is built over diffusion region 16 (used as a bottom plate) with a single thick oxide 17, used as the capacitor cell dielectric, followed by a doped poly layer 18 serving as a top plate. Diffusion region 16 is in turn connected to diffusion region 14. In order to program this capacitor as a fusible link a large external supply between 10-20 V must be applied between capacitor plates 16 and 18 via connecting nodes 20 and 15. As shown in FIG. 2, the external supply V.sub.PP is applied via resistor 25 and, with the appropriate logic, fusible link 22 establishes a conductive path from plate 16 to plate 18 by break down of dielectric 17 (of FIG. 1). Of course, both programming tools, supply V.sub.PP and resistor 25, are removed from the circuitry once programming is accomplished. In addition current/voltage limiter circuit 24 must be fabricated into the integrated circuit containing the device in order to protect the programmed fusible link from any high surge of current that could open the conductive path established between plates 16 and 18 and thus render the device useless. This programming method is not only costly and inefficient but is impractical for use in DRAMs of high density such as the 1 Meg and beyond, due to the excessive real estate required and the lack of readily available planar capacitors.
U.S. Pat. No. 4,881,114 develops a programmable antifuse element out of two conductive layers separated by a multiple dielectric layer for use in PROMs. The concepts and disadvantages are much the same as those in U.S. Pat. No. 4,543,594 except, as shown in FIG. 3, cell dielectric 46 is made of oxide/nitride/oxide (ONO) layers. The programmable element of U.S. Pat. No. 4,881,114 is a planar structure which requires a programming voltage in the neighborhood of 30 V, which means an external supply is required.